pdu10256h 8-bit, ecl-interfaced programmable delay line (series pdu10256h) features packages ? digitally programmable in 128 delay steps ? monotonic delay-versu s-address variation ? precise and stable delays ? input & outputs fully 10kh-ecl interfaced & buffered ? fits 48-pin dip socket pin descriptions in signal input out signal output a0-a7 address bits enb output enable vee -5 volts gnd ground functional description the pdu10256h-series device is an 8-bit digita lly programmable delay line. the delay, td a , from the input pin (in) to the output pin (out) depends on t he address code (a7-a0) according to the following formula: td a = td 0 + t inc * a where a is the address code, t inc is the incremental delay of the device, and td 0 is the inherent delay of the device. the incremental delay is specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. the enable pin (enb) is hel d low during normal operation. when this signal is brought high, out is forced into a low state. the address is not latched and must remain asserted during normal operation. series specifications d a ta delay devices, i n c. ? 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 n/c n/c ou t gn d en b n/c n/c n/c gn d en b n/c n/c n/c n/c n/c n/c n/c gn d en b in n/c n/c a 2 a 1 vee a 0 n/c a 5 a 4 vee a 3 n/c n/c n/c n/c n/c n/c a 7 vee a 6 gn d in a6 vee gn d en b a0 vee 48 47 42 41 1 2 7 8 gn d ou t a 1 a 2 gn d a3 vee 40 34 33 9 15 16 gn d a 4 a 5 32 25 17 19 23 24 gn d a 7 p p p d u 10256h - x x c 5 s m d p d u 10256h - x x m c 5 m i l s m d d u 10256h - x x d i p d u 10256h - x x m m i l d i p dash number specifications part number incremental delay per step (ns) total delay (ns) pdu10256h-.5 0.5 0.3 127.5 6.4 pdu10256h-1 1.0 0.5 255 12.8 pdu10256h-2 2.0 0.5 510 25.5 pdu10256h-3 3.0 1.0 765 38.2 pdu10256h-4 4.0 1.0 1020 51.0 pdu10256h-5 5.0 1.5 1275 63.8 pdu10256h-6 6.0 1.5 1530 76.5 pdu10256h-8 8.0 2.0 2040 102 pdu10256h-10 10.0 2.0 2550 128 note: a n y dash number betw een .5 and 10 not show n is also av ailable. ? total programmed delay tolerance: 5% or 2ns, whichever is greater inherent delay (td 0 ): 12ns typical ? setup time and propagation delay : address to input setup (t ai s ): 3.6ns disable to output delay (t diso ): 1.7ns typical ? operating temperature: 0 to 70 c ? temperature coefficient: 100ppm/ c (excludes td 0 ) ? supply v o ltage v ee : -5vdc 5% ? pow e r dissipation: 925mw typical (no load) ? minimum pulse w i dth: 16% of total delay ? 2009 data delay dev i ces doc #97047 data delay devices, inc. 1 2/9/2009 3 mt. prospect ave. clifton, nj 07013
pdu10256h application notes address update the pdu10256h is a memory device. as such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. the timing restrictions are shown in figure 1. after the last signal edge to be delayed has appeared on the out pin, a minimum time, t oax , is required before the address lines can change. this time is given by the following relation: t oax = max { (a i - a i-1 ) * t inc , 0 } where a i-1 and a i are the old and new address codes, respectively. violat ion of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the out pin. the possibility of spurious signals persists until the required t oax has elapsed. a similar situation occurs when using the enb signal to disable the output while in is active. in this case, the unit must be held in the disabled state until the device is able to ?clear? itself. this is achieved by holding the enb signal high and the in signal low for a time given by: t dish = a i * t inc violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the out pin. the possibility of spurious signals persists until the required t dish has elapsed. input restrictions there are three types of restrictions on input pulse width and period listed in the ac characteristics table. the recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. the suggested conditions are those for which signals will propagate through the unit without significant distortion. the absolute conditions are those for which the unit will produce some type of output for a given input. when operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. however, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. in other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. please consult the technical staff at data delay devices if your application has specific high-frequency requirements. please note that the increment tolerances listed represent a design goal. although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. monotonicity is, however, guaranteed over all addresses. t dis o t oax t aen s t en i s pw in td a pw ou t t dis h a7 -a0 en b in ou t figur e 1 : t i m i ng d i a g r a m a i-1 a i t ai s doc #97047 data delay devices, inc. 2 12/17/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
pdu10256h doc #97047 data delay devices, inc. 3 12/17/97 3 mt. prospect ave. clifton, nj 07013 device specifications table 1: ac characteristics parameter symbol min typ units total programmable delay td t 127 t inc inherent delay td 0 12.0 ns disable to output low delay t diso 1.7 ns address to enable setup time t aens 1.0 ns address to input setup time t ais 3.6 ns enable to input setup time t enis 3.6 ns output to address change t oax see text disable hold time t dish see text absolute per in 12 % of td t input period suggested per in 32 % of td t recommended per in 200 % of td t absolute pw in 6 % of td t input pulse width suggested pw in 16 % of td t recommended pw in 100 % of td t table 2: absolute maximum ratings parameter symbol min max units notes dc supply voltage v ee -7.0 0.3 v input pin voltage v in v ee - 0.3 0.3 v storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 3: dc electrical characteristics (0c to 75c) parameter symbol min typ max units notes high level output voltage v oh -1.020 -0.735 v v ih = max,50 : to -2v low level output voltage v ol -1.950 -1.600 v v il = min, 50 : to -2v high level input voltage v ih -1.070 v low level input voltage v il -1.480 v high level input current i ih 475 p a v ih = max low level input current i il 0.5 p a v il = min
pdu10256h doc #97047 data delay devices, inc. 4 12/17/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com package dimensions p d u 10256h -xx (c o m m e r c ial d i p ) p d u 10256h -xxm (m ilitar y d i p ) . 150 . 030 2. 450 t y p . 24 15 . 320 ma x . . 018 ty p . . 400 ty p . . 300 ty p . . 012 t y p . . 020 ty p . 40 33 34 32 25 78 2 48 41 42 1 47 9 19 16 17 23 . 600 . 100 . 700 . 800 1. 400 1. 600 2. 200 . 075 1. 500 1. 800 2. 300 pd u 10256h - xxc 5 ( c ommercial sm d ) pd u 10256h - xxm c 5 ( m ilit ary sm d ) 2. 080 . 020 . 882 .0 0 . 020 ty p . . 040 ty p . . 100 . 090 1. 100 . 320 ma x . . 590 ma x . . 010 . 002 . 050 .0 1 . 710 .0 0 . 007 .0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
pdu10256h delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 50 ? to -2v supply voltage (vcc): -5.0v 0.1v c load : 5pf 10% input pulse: standard 10kh ecl threshold: (v oh + v ol ) / 2 levels (rising & falling) source impedance: 50 ? max. rise/fall time: 2.0 ns max. (measured between 20% and 80%) pulse width: pw in = 1.5 x total delay period: per in = 10 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. out out tr i g in re f tr i g t est s e t u p de v i ce unde r t est (d u t ) os ci l l o s c op e pu l s e ge ne ra t o r in ad d r ess sel ec t t i mi n g di ag ram f o r t est i n g t ris e t fa l l per in pw in t ris e t fa l l 20% 20% 50% 50% 80% 80% 50% 50% v ih v il v oh v ol in p u t s ign a l ou tp u t s ign a l doc #97047 data delay devices, inc. 5 12/17/97 3 mt. prospect ave. clifton, nj 07013
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